1. Field of the Invention
This invention relates generally to multiplier circuits and more particularly to a high speed, asynchronous, sequential add multiplier.
2. Description of the Prior Art
High speed digital multiplication is often required for real time computer processing for such tasks as digital filtering, signal processing, and fast Fourier transforms. Synchronous iterative add-shift techniques are not well suited for applications in which speed is a critical factor. Therefore, array multipliers have been developed for asynchronously generating the product of two numbers. One such multiplier circuit is discussed by Douglas Geist, "MOS Processor Picks Up Speed With Bipolar Multipliers", Electronics, Mar. 31, 1977, pages 113-115.
A desirable feature of a multiplier circuit is the ability to perform multiplication upon numbers represented in various number systems. In some applications the numbers input to the multiplier circuit are represented as absolute values (straight-magnitude form). In other so called sign-magnitude applications, a sign bit is coupled with the magnitude portion of the number to designate positive and negative magnitudes. In still other applications, two's-complement number representation is used to represent both positive and negative numbers. One advantage of two's complement notation is that subtraction of a first number from a second number can be performed by adding the two's complement of the first number to the second number, thereby eliminating the need for a subtractor. As magnitude, sign magnitude, and two's complement number systems are well known in the art, they will not be further described. For a more detailed review of binary number systems, see generally Gear, Computer Organization and Programming, McGraw-Hill Book Company, 1969.
Applications may exist in which both straight magnitude and two's complement numbers are to be multiplied by the same multiplier circuit. Prior art array multiplier circuits are not designed so as to allow the multiplier to be programmable, i.e., to be switched between straight magnitude and two's complement operation. Thus, it will be appreciated that an array multiplier which can be selectively controlled to interpret a given plurality of input bits as either a straight magnitude or two's complement number amounts to a significant improvement over the prior art.
Another desirable feature of a multiplier circuit is a provision for expansion of a plurality of such circuts into an array for multiplying numbers with bit lengths which exceed the capacity of a single multiplier circuit. As the standard bit length of computer data words continues to increase, the need for larger multiplier arrays becomes more important. Fabrication of a commercially practical monolithic high speed multiplier circuit is limited, by present integrated circuit technology, to a circuit capable of multiplying two sixteen-bit operands.
Prior art multiplier circuits are known which allow for interconnection to like circuits to form an expanded multiplier array. In forming an expanded array, each of the operands is divided into segments, each segment having a bit length equal to the capacity of a single multiplier circuit. When the operands are in two's complement form, the most significant bit (sign bit) of an operand indicates whether the operand is positive or negative. If the operand is negative then correction terms must be generated within the multiplier circuit in order to provide a proper two's complement product. Prior art multiplier circuits include additional input terminals which are used only to receive the two's complement sign bit of each operand. However, these additional input terminals must be hardwired to a logic "0" for those multiplier circuits within the array that do not receive the two's complement sign bit of the operands. These additional input terminals are coupled to adder circuits for adding correction terms in a two's complement multiplication. For those lower order multiplier circuits for which the additional input terminals have been hardwired to a logic "0", the adder circuits used to add the correction terms are idle. Thus, it will be appreciated that a multiplier circuit which may easily be expanded into a large multiplier array and which does not require the addition of extra adder circuits internally for adding correction terms during a two's complement multiplication is a significant improvement over the prior art.